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W631GG6KB
V DD or V DDQ
V SEH min
V SEH
V DD /2 or V DDQ /2
CK or DQS
V SEL max
V SEL
V SS or V SSQ
time
Figure 91 – Single-ended requirement for differential signals
Note that, while ADD/CMD and DQ signal requirements are with respect to V REF , the single-ended
components of differential signals have a requirement with respect to V DD /2; this is nominally the
same. The transition of single-ended signals through the AC-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach V SEL max, V SEH min has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
10.6.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the
requirements in Table 22. The differential input cross point voltage V IX is measured from the actual
cross point of true and complement signals to the midlevel between of V DD and V SS .
V DD
CK#, DQS#
V IX
V DD /2
V IX
V IX
CK, DQS
V SEH
V SEL
V SS
Figure 92 – V IX Definition
Table 22 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600 & DDR3-1866
MIN. MAX.
UNIT
NOTES
Differential Input Cross Point Voltage
relative to V DD /2 for CK, CK#
Differential Input Cross Point Voltage
relative to V DD /2 for DQS, DQS#
V IX(CK)
V IX(DQS)
- 150
- 175
-150
150
175
150
mV
mV
mV
2
1
2
Publication Release Date: Dec. 09, 2013
Revision A05
- 105 -
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